Preface Acknowledgment About the Author 1. Active devices and modeling 1.1. MOSFET device modeling 1.2. LDMOSFETs 1.2.1.

Small-signal equivalent circuit 1.2.2. Nonlinear I - V models 1.2.3. Nonlinear C - V models 1.2.

4. Charge conservation 1.2.5. Gate-source resistance 1.2.6. Temperature dependence 1.

3. Equivalent circuits characterizing device input and output impedances 1.4. GaAs MESFETs and GaN HEMTs 1.5. BJTs and HBTs 1.5.1.

Nonlinear BJT and HBT models 1.5.2. Determination of equivalent circuit elements 1.5.3. Nonlinear bipolar device modeling 1.5.

4. Large-signal collector capacitance References 2. Impedance matching 2.1. Conjugate matching condition 2.2. Matching with lumped elements 2.2.

1. Analytic design technique 2.2.2. Low-pass and high-pass L-type transformers 2.2.3. - and T-type transformers 2.

2.4. Equal- Q broadband matching 2.3. Matching with transmission lines 2.3.1. Transmission-line transformer 2.

3.2. λ /4 and λ /8 impedance transformers 2.3.3. Low-pass L- and -transformers with series transmission line 2.3.4.

Matching networks with lumped and distributed elements 2.3.5. Equal- Q broadband matching 2.3.6. Broadband matching with stepped transmission lines 2.4.

Lossy match design technique 2.5. Broadband matching with prescribed amplitude-frequency response References 3. Power amplifier design fundamentals 3.1. Power gain and maximum operating frequency 3.2. Power gain and stability 3.

2.1. Immittance approach and stability factor 3.2.2. Frequency domains of BJT potential instability 3.2.3.

Frequency domains of MOSFET potential instability 3.2.4. Parametric oscillations 3.2.5. Examples of stabilization circuits 3.3.

Classes of operation 3.3.1. Conduction angle 3.3.2. Basic classes of operation: A, AB, B and C 3.3.

3. Mixed-mode Class B 3.3.4. Classes of operation based on finite number of harmonics 3.4. Load line and output impedance 3.5.

Bias circuits for HBT power amplifiers 3.6. Power combiners/dividers 3.6.1. Wilkinson power dividers/combiners 3.6.2.

Branch-line hybrid couplers 3.6.3. Coupled-line directional couplers References 4. High-efficiency power amplifier design 4.1. Class-F circuit design 4.1.

1. Idealized Class-F mode 4.1.2. Class F with quarterwave transmission line 4.1.3. Effect of saturation resistance 4.

1.4. Load networks with lumped and distributed parameters 4.1.5. Broadband capability of Class-F power amplifiers 4.2. Inverse Class F 4.

2.1. Idealized inverse Class-F mode 4.2.2. Inverse Class F with quarterwave transmission line 4.2.3.

Load networks with lumped and distributed parameters 4.2.4. Design examples of inverse Class-F GaN HEMT power amplifiers for cellular systems 4.3. Class E with shunt capacitance 4.3.1.

Optimum load-network parameters 4.3.2. Matching with standard load 4.3.3. Effect of saturation resistance and finite switching time 4.3.

4. Optimum, nominal, and off-nominal Class-E operation 4.3.5. Load network with transmission lines 4.4. Parallel-circuit Class E 4.4.

1. Optimum load-network parameters 4.4.2. Operation beyond maximum Class-E frequency 4.4.3. Two-harmonic approximation 4.

4.4. Load network with transmission lines 4.4.5. Power gain 4.4.6.

General case of Class E with finite dc-feed inductance 4.5. Class E with shunt capacitance and shunt filter 4.5.1. Optimum load-network parameters 4.5.2.

ADS simulation setup 4.5.3. Load network with transmission lines 4.6. Summary: magic of parallel circuits 4.7. Summary: comparison of output impedances and load-network parameters 4.

8. Design example: two-stage high-efficiency 1.75-GHz MMIC HBT power amplifier using parallel-circuit Class-E mode 4.9. Broadband Class-E power amplifiers 4.9.1. Reactance compensation technique 4.

9.2. Reactance compensation with quarterwave line 4.9.3. Broadband parallel-circuit Class E 4.9.4.

Broadband Class E with shunt capacitance and shunt filter References 5. High-efficiency oscillator design 5.1. Oscillator basic structures 5.2. Empirical optimum design approach 5.3. Analytic optimum design approach 5.

3.1. Parallel and series feedback oscillators 5.3.2. Optimum oscillation conditions 5.3.3.

Optimum MOSFET oscillator 5.4. High-efficiency design techniques 5.4.1. Class-C operation mode 5.4.2.

Class-F and inverse Class-F oscillators 5.4.3. Class-E power oscillators: from RF to millimeter waves 5.4.4. Load-independent Class-E power oscillator 5.5.

Class-E power oscillators for WPT systems 5.6. Design example: parallel-circuit Class-E oscillator for compact fluorescent lamps References 6. High-efficiency Doherty amplifiers 6.1. Conventional Doherty architecture 6.1.1.

Basic structures 6.1.2. Operation principles 6.1.3. Offset lines 6.2.

Asymmetric Doherty amplifiers 6.3. Multistage Doherty amplifiers 6.3.1. Three-stage structure 6.3.2.

Four-stage architecture (Doherty-in-Doherty) 6.4. Inverted Doherty amplifiers 6.5. Three-way inverted Doherty amplifier with enhanced backoff region 6.6. Integrated and monolithic Doherty amplifiers 6.6.

1. Equivalent circuits with lumped elements and transmission 6.6.2. Integrated Doherty amplifiers 6.6.3. Monolithic Doherty amplifiers 6.

7. Multiband and broadband capability 6.7.1. Dual-band parallel Doherty architecture 6.7.2. Tri-band inverted Doherty configuration 6.

8. Design example: high-power 3.4-3.8 GHz asymmetric inverted GaN HEMT Doherty amplifier for base station applications 6.9. Design examples: integrated sub-6 GHz two-stage GaN HEMT Doherty amplifiers for massive MIMO applications References 7. Mixed-mode and alternative efficiency enhancement techniques 7.1.

Class-FE power amplifiers 7.2. Class-E/F3 power amplifiers 7.2.1. Optimum load-network parameters 7.2.2.

Class E/F3 with lumped elements 7.2.3. Class E/F3 with transmission lines 7.2.4. Class E/F3 with series tank circuit and shunt filter 7.2.

5. Parallel-circuit Class E/F3 7.3. Class-E/F3 oscillators 7.4. Switched-path and load-modulated balanced power amplifiers 7.5. Three-way Doherty amplifier with three-coupled-line combiner 7.

6. Envelope tracking for cellphone applications References.